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Sensor control timing simulation

Image Aggregation
  •  6 sensor frames aggregated in the mux FPGA

  •  Sensor data buffered in FIFO and stored in DDR memories

  •  9M Pixels transferred on XAUI at frame 25 fps 

High BW XAUI transfer                                                                      Imaging system timing

FFT-Based Acquisition
  •  FTTW based algorithms for fast acquisition

  •  2/10ms of RAW data captured by the PCI Express

CMOS Imager Control
  •  Sensor control signals and data acquisition

  •  50 channels serial ADC multiplexing

  •  60 fps frame rate

  •  14 bits pixel resolution data out 

Readout / Exposure timing​

Sensor FPGA design

Mux FPGA design

Time domain and histogram                                                                                                 PRN 20 acquired with high quality CN0

Linux Shell showing the acquired satellites  PRN, Code, Doppler

Acquired L1 Satellites 

Tracking Engines on FPGA
  •  GPS L1 tracking channel from concept to RTL design

  •  IQ Mixers, NCO, MAC, PRN code generator

  •  IQ stored in a FIFO and sent through PCI Express

GPS L1 Tracking Channel Architecture                                               GPS L1 Tracking Channel RTL Design

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